The present invention relates to a semiconductor device of a MIS (Metal-Insulator-Semiconductor) structure and a method for fabricating the same, more specifically to a semiconductor device and a method for fabricating the same which can decrease parasitic resistance and improve current-driving performance.
The present invention also relates to a semiconductor device of semiconductor-semimetal structures, and a semiconductor integrated circuit including a plurality of the semiconductor integrated structures laid one on another through inter-layer insulation films.
Semiconductor devices require higher integration and higher speed for further improved performances. To meet such requirements, micronization of constituent elements is essential. Not only micronizing techniques, but also various structures and their fabrication methods for attaining high operation speed of the elements are proposed.
In a transistor of MIS (Metal-Insulator-Semiconductor) structure, which represents MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the element is micronized mainly by decreasing the gate length.
However, as the MOSFET is more micronized, the influence of the drain electric field to the channel region become unignorable, and the phenomena that a threshold voltage rapidly changes with respect to a gate length, the so-called short channel effect becomes a problem. Generation of the short channel effect causes threshold voltage deviation of an ultra-micronized MOSFET, which substantially decreases margins of circuit designs. In addition, with the element micronization, the dopant diffused layer has become extremely shallow. The parasitic resistance component in the source/drain region is a barrier to improving the current-driving performance.
Accordingly, to develop elements, it is very important to suppress the short channel effect accompanying the element micronization and decrease the parasitic resistance.
FIG. 29 shows a diagrammatic sectional view of the typical MIS-type semiconductor device. An SOI substrate is formed of a silicon substrate 200, a silicon oxide film 202 formed on the silicon substrate 200, and a silicon layer 204 formed on the silicon oxide film 202. A gate electrode 208 is formed on the silicon layer 204 interposing a gate insulation film 206 therebetween. A source/drain diffused layers 210 are formed in the silicon layer 204 on both sides of the gate electrode 208. The source/drain diffused layers 210 have respective extension regions 214 directed to a channel region 212, which is immediately below the gate electrode 208.
The semiconductor device shown in FIG. 29 suppress the short channel effect by using the SOI substrate and providing the extension regions 214 in the source/drain diffused layers 210. The extension regions 214 have higher dopant concentration than the lightly doped diffused region of the conventional LDD (Lightly Doped Drain) structure, whereby the source/drain diffused layers 210 has reduced parasitic resistance. However, as the micronization further goes on, even in the semiconductor device shown in FIG. 29 the parasitic resistance of the source/drain diffused layers will be a barrier factor for improving current-driving performance. This structure is being approaching to the limit in terms of processing techniques because further micronization requires the source/drain diffused layers 210 to have abrupt profile.
On the other hand, it is theoretically presumed that SiGeC semiconductor material, which lattice-matches with the silicon substrate, has the band gap narrowed by increasing a carbon (C) concentration and, furthermore, semimetalized (refer to, e.g., M. Ohfuti et al., Extended Abstracts of the 1999 International Conference on Solid State Device and Materials, Tokyo, 1999, pp. 476-477). Then, it is proposed that such semimetalized layer is used in the so-called elevated source/drain structure so as to decrease parasitic resistance (refer to, e.g., Laid-open Japanese Patent Application No. Hei 11-284171, 1999. As exemplified in FIG. 30, in a semiconductor device having an elevated source/drain structure, a semimetal layer 216 of an SiGeC layer is formed on a silicon layer 204 of the source/drain regions. However, in this structure, the semimetal layer 216 is formed across a sidewall insulation film 218 on the side wall of the gate electrode 208, whereby resistance between a channel region 212 immediately below the gate electrode 208 and the semimetal layer 216 cannot be decreased.
Tucker et al. propose a Schottky junction source/drain structure using a metal layer as the extension regions for the end of decreasing the parasitic resistance in source/drain regions. As shown in FIG. 31A, a semiconductor device having the Schottky junction source/drain structure has the source/drain regions formed of a metal layer 220 which is extended down to a channel region 212 immediately below the gate electrode 208. However, in this structure, potential barrier is formed due to the semiconductor-metal junction (Schottky junction) formed between the channel region 212 and the source/drain regions 220, whereby the potential in the channel region increases, and excess resistance is generated. This structure cannot be absolutely good for improving current-driving performance. It is also a disadvantage that in order to nullify the potential, an offset voltage is needed until current starts to flow.
As described above, various structures have been proposed so as to decrease the parasitic resistance in the source/drain regions. However, these structures cannot be sufficient to improve current-driving performance. A semiconductor device which can decrease the parasitic resistance in the source/drain diffused layer regions and further improve current-driving performance has been required.
On the other hand, semiconductor integrated circuits have so far continuously increased integration by scale-down of dimensions and break-through of device structures. However, the micronization of transistors has come to the stage of sub-0.1 micron size, and it has come almost to a limit to maintain the scaling. The limit is conspicuous specifically in processing techniques which cause characteristic deflections, such as gate length deflections, dopant deflections, etc., and in thinning ion-doped layers. Furthermore, it is difficult to continue the micronizing trend, e.g., maintain cell size factors of DRAMs and others as far as the micronization trend relies on the conventional planar device structure.
Presently, for further micronization, the so-called vertical MOS transistor has begun to be proposed (refer to e.g., J. M. Hergenrother et al., IEDM Tech., Dig., p. 75, 1999).
However, a transistor simply formed in a vertical structure can have a decreased gate length but must have a large heavily doped semiconductor region in a lead part from the lower region of the gate electrode to the source/drain electrodes. This causes a problem that parasitic, resistance component in this region is a cause for deteriorating high speed and high frequency characteristics of the transistor.
Furthermore, micronizing elements, retaining their high performances is required not only by simple MOS transistors, but also naturally by semiconductor devices of complicated constitutions including a plurality of transistors having different conduction types, dopant concentrations, etc. connected to one another. Further improvement and development of transistor structures are presently waited.
Higher density of integrated circuits and higher integration and higher performances of systems on chips, etc. are required, and multi-layer interconnection techniques and furthermore three-dimensional integration are being studied (refer to, e.g., M. Koyanagi et al., IEEE MICRO 18(4), p.17, 1998).
As exemplified in FIG. 32, such integrated circuit comprises LSI chips 301 formed in semiconductor integrated structures, which are arranged in multi-layers one on another with inter-layer insulation films 302 respectively disposed between the respective LSI chips 301 and their adjacent one, and are connected to their adjacent one by metal columns 303 called vias buried in the inter-layer insulation films 302.
As semiconductor integrated circuits are more complicated in such multi-layer structures, it is more required to more integrate and more micronize the semiconductor integrated circuits with their high performances retained. Their design freedom is accordingly more required.
A first object of the present invention is to provide a structure of a semiconductor device and a method for fabricating the same which can decrease the parasitic resistance of the source/drain regions and can improve current-driving performance.
A second object of the present invention is to provide a semiconductor device which allows various elements of complicated constitutions having a plurality of different transistors interconnected to one another to be integrated with high density in much reduced occupation areas in comparison with those of planar-type element structures, retaining good high-speed and high-frequency characteristics.
A third object of the present invention is to provide a semiconductor integrated circuit of a complicated multi-layer interconnected constitution including a plurality of integrated circuit structures laid one on another with inter-layer insulation films disposed therebetween, in which vias interconnecting the laid semiconductor integrated structures are given prescribed functions to be used so as to ensure organic interrelation among the respective semiconductor integrated structures in small occupation areas and with very high efficiency and to drastically improve design freedom.
The above-described first object is achieved by a semiconductor device comprising: a channel region formed of silicon; a source region and a drain region respectively forming junction with the channel region; and a gate electrode formed on the channel region interposing an insulation film therebetween, at least one of the source region and the drain region being formed of SiGeC, which lattice-matches with silicon.
In the above-described semiconductor device, it is possible that a junction between the channel region and the source region or the drain region is formed immediately below the gate electrode or the ends of the gate electrode.
In the above-described semiconductor device, it is possible that the gate electrode is formed surrounding the channel region.
In the above-described semiconductor device, it is possible that the gate electrode includes a lower gate electrode and an upper gate electrode, and the low gate electrode and the upper gate electrode are formed, opposed to each other across the channel region.
In the above-described semiconductor device, it is possible that the source region or the drain region is formed of a semimetallic SiGeC containing carbon by above 6%.
The above-described first object also is achieved by a method for fabricating a semiconductor device comprising the steps of: forming a channel region of silicon; and forming a source region or a drain region of SiGeC to respectively form junction with the channel region.
In the above-described semiconductor device, it is possible that the method further comprises, prior to the step of forming the channel region, the steps of: forming a gate insulation film on a substrate having a single crystal layer at least on the surface thereof; and forming a first electrode on the gate insulation film, in the step forming the channel region, the gate insulation film and the silicon layer are etched with the first electrode as a mask to form the channel region of the silicon layer below the gate electrode; and in the step of forming the source region or the drain region, the source region and/or the drain region are epitaxially grown with the channel region as a seed.
In the above-described semiconductor device, it is possible that the method further comprises the steps of: removing the first electrode; and burying a gap formed by removing the first electrode with a second electrode.
In the above-described semiconductor device, it is possible that the method further comprises, prior to the step of forming the channel region, the steps of: forming a gate insulation film on a substrate having a single crystal layer at least on the surface thereof; and forming a gate electrode on the gate insulation film, selectively transforming the silicon layer in regions on both sides of the gate electrode to SiGeC to form the source region and/or the drain region and form the channel region of the silicon layer between the source region and the drain region.
In the above-described semiconductor device, it is possible that the method further comprises, prior to the step of forming the channel region, the steps of: sequentially forming on a silicon substrate, a first gate electrode, a first gate insulation film, a film-to-be-selectively-removed having etching characteristics different from those of the first gate insulation film, a second-gate insulation film having etching characteristics substantially equal to those of the first gate insulation film, and a second gate electrode; selectively removing the film-to-be-selectively-removed; and epitaxially growing a silicon layer with the silicon substrate as a seed to bury a gap between the first gate insulation film and the second gate insulation film with the silicon film, in the step of forming the channel region, the silicon layer being left selectively between the first gate insulation film and the second gate insulation film to form the channel region of the silicon layer, and in the step of forming the source region and/or the drain region, the source region and/or the drain region being epitaxially grown with the channel region as a seed.
The above-described first object also is achieved by a method for fabricating a semiconductor device comprising the steps of: forming on a silicon substrate an insulation film with an opening reaching the silicon substrate; forming a film-to-be-selectively-removed having etching characteristics different from those of the first insulation film on the insulation film and in the opening; forming a gate electrode on the film-to-be-selectively-removed interposing a gate insulation film therebetween; removing the film-to-be-selectively-removed; and epitaxially growing, with the silicon substrate exposed in the opening as a seed, continuously a source region of SiGeC, a channel region of silicon forming junction with the source region and a drain region forming junction with the channel region.
The above-described first object is also achieved by a method for fabricating a semiconductor device comprising the steps of: epitaxially growing on a substrate having a single crystal silicon layer at least on the surface thereof, continuously a source region of SiGeC, a channel region of silicon forming junction with the source region, and a drain region forming junction with the channel region; forming a gate insulation film, surrounding the channel region; and forming a gate electrode surrounding the channel region interposing the gate insulation film therebetween.
In the semiconductor device according to the present invention comprising the channel region of silicon, the source region and the drain region respectively forming a junction with the channel region, the gate electrode formed on the channel region interposing the insulation film therebetween, at least one of the source region and the drain regions is formed of SiGeC, which lattice-matches with silicon, whereby parasitic resistance in the region can be reduced because of a number of carriers of the semimetallic SiGeC.
The composition graded layer is provided between the channel region and the source/drain regions, whereby potential changes in the junction interface can be smooth, and the parasitic resistance can be further reduced.
Accordingly, the semiconductor device according to the present invention can provide a high-speed, high-frequency MOS transistor having no potential barrier between the source region and the channel region and between the drain region and the channel region, and having abrupt doping profile provided by the crystal growth.
The second object of the present invention is achieved by a semiconductor device comprising: a layered structure including: a first semimetal layer; a first semiconductor layer formed on the first semimetal layer; a second semimetal layer formed on the first semiconductor layer; a second semiconductor layer formed on the second semimetal layer; and a third semimetal layer formed on the second semiconductor layer; a first gate electrode for controlling a current between the first semimetal layer and the second semimetal layer through the first semiconductor layer; and a second gate electrode for controlling a current between the second semimetal layer and the third semimetal layer through the second semiconductor layer, the first semiconductor layer and the second semiconductor layer having substantially the same lattice constant as the first to the third semimetal layers or being thin sufficiently to prevent occurrence of crystal defects even when a lattice constant: disagree with the first to the second semimetal layers.
The semiconductor device has as a basic structure the semiconductor-semimetal structure comprising a semiconductor layer which is thin sufficiently to prevent occurrence of crystal defects even when a lattice constant agrees or does not agree, a first semimetal layer and a second semimetal layer, the semiconductor layer being sandwiched between the first and the second semimetal layers, the semiconductor layer forming a gate electrode, and the first and the second semimetal layers forming the ohmic electrodes. At least two basic structures are laid one on another to form a required semiconductor device, such as a vertical complementary MOS inverter structure, a vertical transmission gate structure, an E/D logic gate structure, or others.
Thus, the semiconductor device according to the present invention comprises the basic structures laid three-dimensionally one on another, whereby the semiconductor device can be provided in a layer structure in which a plurality of transistors of good high-speed and high-frequency characteristics complicatedly interconnected in a relatively simple layer structure and in a very small occupied area which does not much add to an occupied area of one basic structure.
According to the present invention, various elements of complicated structures including a plurality of different transistors interconnected to one another can have much decreased occupied areas and higher integration with higher density in comparison with the planar element structures, maintaining good high-speed and high-frequency characteristics.
The third object of the present invention is achieved by a semiconductor integrated circuit including a plurality of semiconductor integrated structures laid one on another interposing inter-layer insulation films therebetween, comprising: a via buried in the inter-layer insulation film for electrically connecting the different semiconductor integrated circuit structures, the via having a first semimetal layer; a second semimetal layer; a semiconductor layer having substantially the same lattice constant as the first and the second semimetal layer or being thin sufficiently to prevent occurrence of crystal defects even when a lattice constant disagree with the first and the second semimetal layer, the semiconductor layer being sandwiched between the first and the second semimetal layers; and a gate electrode for controlling a current between the first semimetal layer and the second semimetal layer through the semiconductor layer.
The semiconductor integrated circuit of the present invention is an integrated circuit in which a plurality of semiconductor integrated structures are laid one on another through inter-layer insulation films. In the integrated circuit, vias buried in the inter-layer insulation films and electrically connecting the different semiconductor integrated structures provide the basic structures.
In the semiconductor integrated circuit according to the present invention, the basic structure of the transistor is applied to the vias electrically interconnecting the semiconductor integrated structures, whereby the vias can be used not only the mere connection means, but also as the elements having various positive functions in addition to the connection function, e.g., switching function.
According to the present invention, an integrated circuit of a complicated multi-layer interconnection structure including a plurality of semiconductor integrated structures laid one on another through inter-layer insulation films can ensure organic relationship among the respective semiconductor integrated structures very effectively at a small occupied area and drastically increase design freedom by using vias interconnecting semiconductor integrated structures laid one on another and giving prescribed functions to the vias.